Bond pads are use in integrated circuits (ICs) to electrically connect the integrated circuit to external components. Small, simple ICs typically have a few pads, while complex digital ICs can have well over 1000 pads. The IC die is often coated with layers of silicon dioxide (SiO2) and silicon nitride (Si3N4) dielectric to prevent mechanical damage and moisture ingress, except at the pad openings where the aluminum (Al) film of the bond pad is exposed. The pad opening is also commonly referred to as a “passivation window” or “nitride window”.
Below this top coating are interleaved layers of dielectric (typically SiO2) and metallization with fine horizontal (i.e., in the plane of the metallization layer) metal interconnect circuitry. The metallization is often primarily aluminum with perhaps a top and bottom coating of titanium nitride (TiN). The dielectric layers electrically separate neighboring metallization layers except at conductive vias that extend vertically (perpendicular to the plane of the metallization and dielectric layers) to electrically connect one metallization layer to another. Such vias are often composed of tungsten (W).
Two to seven individual metallization layers are common in aluminum metallization technologies, depending upon the complexity of the IC. The semiconductor “devices” such as transistors and diodes are at the silicon (Si) wafer surface, beneath the dielectric layers and metallization layers. Such devices are covered in dielectric, with W contacts that connect them electrically to wires typically in the first metallization layer. Below the semiconductor devices is the relatively thick silicon (Si) body that provides the rigid structural strength of the die.
Pad structures consist of the bond pad itself and all the material beneath the pad opening. In the traditional pad structure, interconnect wiring or the usual semiconductor devices are not present beneath the pad opening, where the Al pad film of the bond pad is exposed. The traditional pad structure in this metallization system consists of a stack of ductile Al films sandwiched between brittle SiO2 glass films that are prone to crack as they bend.
Other circuitry in the IC has traditionally been designed to be relatively far away from the pad structures to avoid reliability risks. However, as IC die area continues to be reduced, designs have brought circuitry closer to and even under the pads, potentially increasing reliability risks due to the latent damage caused by wafer probing and wirebonding.
Some prior designs acknowledge that cracks will occur, and aim to contain the cracks within the region of the upper pad films. The occurrence of cracks and other pad damage affecting reliability are recognized as being more serious as interconnect circuitry replaces the full metal plates beneath the pad window, especially in the top-metal-minus-one (or metal top-minus-one, MT(−1)) layer. As mentioned, most prior efforts revolve around methods of probing and bonding more gently, thus reducing the stress applied to the pad.
The most common pad structure improvement methods are to remove the top vias from beneath the pad window for crack prevention, and to thicken the Al pad film layer to help dissipate stress at the top of the pad structure rather than directly transferring it below the pad metal. Other than these, the reported methods can be roughly placed into two categories: 1) modifications to the films near the top of the pad, and 2) employment of special structures in the pad sub-layers to achieve a specific purpose.